The present invention relates to a method for fabricating a semiconductor device; and, more particularly, to a method for fabricating a semiconductor device with ultra-shallow super-steep-retrograde epi-channel of which gate length is less than 100 nm.
Generally, in such transistors as metal-oxide-semiconductor field effect transistor (MOSFET) or metal-insulator-semiconductor field effect transistor (MISFET), a surface area of a semiconductive substrate, allocated below a gate electrode and a gate oxide layer, functions to flow electric circuits via an electric field supplied to a source and/or a drain in a state of supplying a voltage to the gate electrode. Thus, this surface area is called as a channel.
Also, properties of the above transistors rely on a dopant concentration of a channel, and a precise doping of the channel is very important since the dopant concentration determines several properties such as a threshold voltage of the transistor (VT), a drain current (Id) and so forth.
In connection to techniques for precise doping of the channel, ion implantation techniques including a well ion implantation and a channel ion implantation (alias; a threshold-voltage-adjusting ion implantation) are commonly used. The ion implantation technique is capable of forming the channel in variously diverse structures. As examples of the possible channel structures, there are a flat channel structure that has a uniform channel doping concentration keeping in depth within it, the buried channel structure wherein the channel formation occurs in a certain depth and a retrograde channel structure, wherein the channel doping concentration increases in depth.
Among the above-mentioned channels, the retrograde channel is formed by using such heavy ions as indium (In), arsenic (As) and antimony (Sb) and so forth through heavy ion implantation techniques and is generally used for a highly functioned microprocessor of which the gate length is less than 0.2 xcexcm. Also, the retrograde channel is applied to a highly functioned device having a property of a high driving current since the retrograde channel shows an effect of increasing a the surface mobility with decreasing the doping concentration of surface.
As a gate length has been decreased, a channel depth is required to become shallower. Thus, it is limited for applying the ion implantation technique to a channel of which depth is less than 50 nm.
In order to improve this limitation, an epi-channel structure had been suggested wherein the epi-channel is formed on a channel doping layer.
FIG. 1A is a view illustrating an epi-channel structure of a semiconductor device in accordance with the prior art.
As shown in FIG. 1A, a gate oxide layer 12 and a gate electrode 13 are formed on a substrate 11, and an epi-channel including an epi-layer 14 and a channel doping layer 15 is formed on the substrate 11 allocated below the gate oxide layer 12. On lateral sides of the epi-channel, a highly concentrated source/drain extension (hereinafter referred as SDE) 16 and a source/drain area 17 are formed as well.
However, it is impossible for the above described prior art to establish an improved on/off current targeted by the semiconductor device with the epi-channel structure since it is difficult to control the loss and the diffusion of dopants from the channel doping layer 15.
As shown in FIG. 1B, another approach has been proposed for establishing a step-like xcex4-doped epi-channel to solve the above problem of the prior art.
FIG. 1B is a diagram showing changes of a doping profile of the xcex4-doped epi-channel in accordance with a transient enhanced diffusion (hereinafter referred as to TED) or a thermal budget. Also, it is observed that the xcex4-doped profile is broadening because the step-like xcex4-doping profile of the epi-channel allocated below the gate oxide layer 12 is unable to maintain a preferable xcex4-doping profile due to the TED or the excessive thermal budget. Herein, the broadening of the xcex4-doping profile and the preferable xcex4-doping profile are expressed as P2 and P1 in FIG. 1B, and the gate oxide layer 12 is abbreviated as Gox.
Accordingly, although a xcex4-doped epi-channel with doped and undoped epi-layers is formed, it is still limited to establish a xcex4-doped epi-channel of which depth is less than 30 nm as dopants are diffused due to the TED or the excessive thermal budget. The dopant profile after excessive diffusion of the xcex4-doped dopants are shown as D in FIG. 1B.
As one solution for this limitation, it is suggested to restrain the diffusion of the xcex4-doped epi-channel by instantaneously performing a laser thermal annealing (hereinafter referred as to LTA) process after forming the xcex4-doped channel doping layer 24 in FIG. 2A. With a required concentration through an ultra low energy ion implantation technique. FIGS. 2A and 2B are cross-sectional views illustrating the above described method.
With reference to FIGS. 2A and 2B, it is described a method of prior art for fabricating a semiconductor device with an epi-channel by the ultra low energy ion implantation and the LTA techniques.
Referring to FIG. 2A, P-type dopants are ion implanted on a substrate 21 formed with a field oxide layer 22 in a shallow trench isolation (STI) structure so as to form a deep P-type well 23. Subsequently, boron ions having about 1 keV of the ultra low energy are implanted thereto, forming a xcex4-doped channel doping layer 24.
Next, the LTA with a unit energy level ranging from about 0.36 J/cm2 to about 0.44 J/cm2 is directly performed without preceeding a pre-amorphization process for making a surface of the substrate 21 amorphous. FIG. 2B shows the result from a direct application of the LTA, in which boron ions are redistributed forming the resultant xcex4-doping layer 24A with the suppression of TED.
Referring to FIG. 2B, an epi-layer 25 is formed through a selective epitaxial growth (hereinafter referred as to SEG) on the channel doping layer 24A so as to form a super-steep-retrograde (hereinafter referred as to SSR) epi-channel structure. The thickness of above epi-layer 25 ranges from about 50 xc3x85 to about 300 xc3x85, formed at a temperature ranging from about 600xc2x0 C. to about 800xc2x0 C. Meanwhile, it is also possible to suppress the TED of the xcex4-doped channel doping layer 24 through a rapid thermal annealing (hereinafter referred as to RTA) in addition to the LTA.
FIG. 3A is a graph showing a doping profile of the SSR epi-channel formed by the selective epitaxial growth on the sample doped with boron ions (B+) in 1 keV, while FIG. 3B is a graph showing a doping profile of the SSR epi-channel formed by the selective epitaxial growth on the sample doped with boron ions (B+) in 5 keV.
Referring to FIGS. 3A and 3B, with respect to the doping profile of the SSR epi-channel through the ultra low energy ion implantation, as lowering the ion implantation energy, a distribution range of the xcex4-doping becomes narrower, and this narrow distribution of the xcex4-doping can reduce significantly a junction capacitance of a semiconductor device. Also, it is possible to decrease the leakage currents of the junction, thereby ultimately manufacturing a semiconductor device with a low consumption of electricity and high efficiency. Therefore, this ultra low energy ion implantation technique is an essential technology to produce the above functioned semiconductor.
However, the ultra low energy ion implantation technique has a difficulty in extracting ion beams at the ultra low energy, and this difficulty results in limiting usable energies and in low productivity for establishing the doping profile for the SSR epi-channel.
It is, therefore, an object of the present invention to provide a method for fabricating semiconductor devices with epi-channel structure that overcome the limitations in useable energy and the decrease of productivity when employing a ultra low energy ion implantation technique which has a disadvantage in prolonged processing time.
In accordance with an aspect of the present invention, there is provided a method for fabricating a semiconductor device with ultra shallow super-steep-retrograde (hereinafter referred as to SSR) epi-channel, comprising the steps of: forming a channel doping layer below a surface of a semiconductor substrate by implanting decaborane; forming an epi-layer on the channel doping layer; forming sequentially a gate dielectric layer and a gate electrode on the epi-layer; forming source/drain extension areas shallower than the channel doping layer by being aligned at edges of the gate electrode; forming a spacers on lateral sides of the gate electrode; and forming source/drain areas deeper than the channel doping layer by being aligned at edges of the spacer through ion implantation onto the substrate.
In accordance with another aspect of the present invention, there is provide a method for fabricating a semiconductor device with ultra shallow super-steep-retrograde (hereinafter referred as to SSR) epi-channel, comprising the steps of: forming a well in semiconductive substrate; forming a first punch stop doping layer by implanting decaborane ions below a surface of above the well; performing a first annealing process at a temperature lower than a melting point of the substrate; forming an epi-layer on the punch stop doping layer; forming sequentially a gate dielectric layer and a gate electrode on the epi-layer; forming a first source/drain area aligning at both edges of the gate electrode; forming a second punch stop doping layer below the first source/drain area by implanting the same dopant in the well; forming a second source/drain area connected to the first source/drain area and deeper than the first source/drain area; and performing a second annealing process for the purpose of activation of dopants in the first and the second source/drain area at a temperature suppressing the diffusions of the channel doping layer.
In accordance with further aspect of the present invention, there is also provided a method for fabricating a semiconductor device with ultra shallow super-steep-retrograde (hereinafter referred as to SSR) epi-channel, comprising the steps of: forming a well in semiconductive substrate; forming a first punch stop doping layer by implanting decaborane ions below a surface of above the well; performing a first annealing process at a temperature lower than a melting point of the substrate; forming an epi-layer on the punch stop doping layer; forming sequentially a gate dielectric layer and a gate electrode on the epi-layer; forming a first source/drain area aligning at both edges of the gate electrode; forming a second punch stop doping layer below the first source/drain area by implanting the same dopant in the well; forming a second source/drain area connected to the first source/drain area and deeper than the first source/drain area; and performing a second annealing process for the purpose of activation of dopants in the first and the second source/drain area at a temperature suppressing the diffusions of the channel doping layer.
In addition, the formation of the well is followed by the step of forming a field stop doping layer, same dopant as the well at the depth close to the bottom of field Oxide. Selective epitaxial growth is performed on the second source/drain areas to form a third source/drain areas.